Theoretical metrics such as TOPS frequently fail to predict real-world AI chip performance accurately and to varying degrees, typically overpromise and underdeliver. There is a lot of angst and discussion about this root cause, but an often-overlooked culprit is the clock network, one of the largest networks on an SoC. 

The clock network can be the ultimate gating factor or enabler in data flow on a chip. Data can only move as far as one clock cycle allows. As chips grow larger and approach reticle limits, clock paths also significantly lengthen, further complicating existing clocking problems such as skew and silicon variation (at finer process geometries). An optimized clock network can streamline data flow and raise on-chip interconnect bandwidth.

Standard clock topologies that work well on small chips cannot scale to today’s very large chips. A new approach called intelligent clock networks, delivers an “ideal” clock close to the point of use, simplifying SoC designs and virtually eliminating overhead typically expended for clock distribution. Mo Faisal, the CEO and Founder of Movellus, will examine how intelligent clock networks can usher in a new era of big chip design for AI and HPC applications. Throughout his presentation, Mo will showcase how these new clock network types can help architects reach their architectural goals while generating differentiation in silicon cost and power efficiency in an already crowded market segment.