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Connie Zhang

CEO
Rent|Vest

Decades of working experience spans Data & Analytics | Digital Transformation | FE@MBS/RMBS Prepayment across Banking Finance | Hedge funds | Proptech | FinTech | Pharma. Has built rounds of end-to-end data product with DM/DG & AI/ML capability with data standardization over 2K data feeds. MBA @ Investment Management, BS and MS @Computer Science & CFA.

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Connie Zhang

CEO
Rent|Vest

Connie Zhang

CEO
Rent|Vest

Decades of working experience spans Data & Analytics | Digital Transformation | FE@MBS/RMBS Prepayment across Banking Finance | Hedge funds | Proptech | FinTech | Pharma. Has built rounds of end-to-end data product with DM/DG & AI/ML capability with data standardization over 2K data feeds. MBA @ Investment Management, BS and MS @Computer Science & CFA.

Author:

Mike Howard

Vice President of DRAM and Memory Markets
TechInsights

Mike has over 15 years of experience tracking the DRAM and memory markets. Prior to TechInsights, he built the DRAM research service at Yole. Prior to Yole, Mike spent time at IHS covering DRAM and Micron Technology where he had roles in engineering, marketing, and corporate development. Mike holds an MBA from The Ohio State University and a BS in Chemical Engineering and BA in Finance from the University of Washington.

 

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Mike Howard

Vice President of DRAM and Memory Markets
TechInsights

Mike has over 15 years of experience tracking the DRAM and memory markets. Prior to TechInsights, he built the DRAM research service at Yole. Prior to Yole, Mike spent time at IHS covering DRAM and Micron Technology where he had roles in engineering, marketing, and corporate development. Mike holds an MBA from The Ohio State University and a BS in Chemical Engineering and BA in Finance from the University of Washington.

 

Author:

Murali Emani

Computer Scientist
Argonne National Lab

Murali Emani is a Computer Scientist in the Data Science group with the Argonne Leadership Computing Facility (ALCF) at Argonne National Laboratory. At ALCF, he co-leads the AI Testbed where they explore the performance, efficiency of novel AI accelerators for scientific machine learning applications. He also co-chairs the MLPerf HPC group at MLCommons, to benchmark large scale ML on HPC systems. His research interests are in Scalable Machine Learning, AI accelerators, AI for Science, and Emerging HPC architectures.  His current work includes

- Developing performance models to identifying and addressing bottlenecks while scaling machine learning and deep learning frameworks on emerging supercomputers for scientific applications.

- Co-design of emerging hardware architectures to scale up machine learning workloads.

- Efforts on benchmarking ML/DL frameworks and methods on HPC systems.

 

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Murali Emani

Computer Scientist
Argonne National Lab

Murali Emani is a Computer Scientist in the Data Science group with the Argonne Leadership Computing Facility (ALCF) at Argonne National Laboratory. At ALCF, he co-leads the AI Testbed where they explore the performance, efficiency of novel AI accelerators for scientific machine learning applications. He also co-chairs the MLPerf HPC group at MLCommons, to benchmark large scale ML on HPC systems. His research interests are in Scalable Machine Learning, AI accelerators, AI for Science, and Emerging HPC architectures.  His current work includes

- Developing performance models to identifying and addressing bottlenecks while scaling machine learning and deep learning frameworks on emerging supercomputers for scientific applications.

- Co-design of emerging hardware architectures to scale up machine learning workloads.

- Efforts on benchmarking ML/DL frameworks and methods on HPC systems.

 

Author:

Nuwan Jayasena

Fellow
AMD

Nuwan Jayasena is a Fellow at AMD Research, and leads a team exploring hardware support, software enablement, and application adaptation for processing in memory. His broader interests include memory system architecture, accelerator-based computing, and machine learning. Nuwan holds an M.S. and a Ph.D. in Electrical Engineering from Stanford University and a B.S. from the University of Southern California. He is an inventor of over 70 US patents, an author of over 30 peer-reviewed publications, and a Senior Member of the IEEE. Prior to AMD, Nuwan was a processor architect at Nvidia Corp. and at Stream Processors, Inc.

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Nuwan Jayasena

Fellow
AMD

Nuwan Jayasena is a Fellow at AMD Research, and leads a team exploring hardware support, software enablement, and application adaptation for processing in memory. His broader interests include memory system architecture, accelerator-based computing, and machine learning. Nuwan holds an M.S. and a Ph.D. in Electrical Engineering from Stanford University and a B.S. from the University of Southern California. He is an inventor of over 70 US patents, an author of over 30 peer-reviewed publications, and a Senior Member of the IEEE. Prior to AMD, Nuwan was a processor architect at Nvidia Corp. and at Stream Processors, Inc.

Author:

Simone Bertolazzi

Principal Analyst, Memory
Yole Group

Simone Bertolazzi, PhD is a Senior Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group, working with the Semiconductor, Memory & Computing division. As member of the Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architectures and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.

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Simone Bertolazzi

Principal Analyst, Memory
Yole Group

Simone Bertolazzi, PhD is a Senior Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group, working with the Semiconductor, Memory & Computing division. As member of the Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architectures and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.

Author:

Nan Ding

Research Scientist
Berkeley Research Lab

Nan Ding is a Research Scientist in the Performance and Algorithms group of the Computer Science Department at Lawrence Berkeley National Laboratory. Her research interests include high-performance computing, performance modeling and performance optimization. Nan received her Ph.D. in computer science from Tsinghua University, Beijing, China in 2018.

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Nan Ding

Research Scientist
Berkeley Research Lab

Nan Ding is a Research Scientist in the Performance and Algorithms group of the Computer Science Department at Lawrence Berkeley National Laboratory. Her research interests include high-performance computing, performance modeling and performance optimization. Nan received her Ph.D. in computer science from Tsinghua University, Beijing, China in 2018.

Author:

Xavier Soosai

Chief Information Officer
Center for Information Technology/National Institute of Health

As the Director of the Office of Information Technology Services of the Center for Information Technology (CIT), Soosai oversees ten service areas and the delivery of scientific research and business operations across the institutes and centers (ICs) at NIH. This includes maintaining the high-performance computing environment used by NIH intramural scientists; maintaining NIH’s secure, high-speed network; ensuring the viability and availability of collaboration services, compute hosting and storage services, identity and access management services, service desk support, and more for the NIH community. 

Soosai works with CIT leadership and internal service area managers and collaborates with NIH ICs to define scope and provide technical expertise, strategic planning, and leadership for local and enterprise IT projects that drive efficiency and innovation across NIH. Additionally, Soosai is responsible for directing the evaluation and adoption of rapidly evolving technology and forecasting future technology needs.

 

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Xavier Soosai

Chief Information Officer
Center for Information Technology/National Institute of Health

As the Director of the Office of Information Technology Services of the Center for Information Technology (CIT), Soosai oversees ten service areas and the delivery of scientific research and business operations across the institutes and centers (ICs) at NIH. This includes maintaining the high-performance computing environment used by NIH intramural scientists; maintaining NIH’s secure, high-speed network; ensuring the viability and availability of collaboration services, compute hosting and storage services, identity and access management services, service desk support, and more for the NIH community. 

Soosai works with CIT leadership and internal service area managers and collaborates with NIH ICs to define scope and provide technical expertise, strategic planning, and leadership for local and enterprise IT projects that drive efficiency and innovation across NIH. Additionally, Soosai is responsible for directing the evaluation and adoption of rapidly evolving technology and forecasting future technology needs.

 

Author:

Rahul Gupta

AI Research Scientist
US Army Laboratory

Dr. Rahul Gupta has been working at the Army Research Lab for more than a decade. In his current position he is conducting research and development using Deep Learning Artificial Neural Network and Convolutional Neural Network. He joined ARL as a Distinguished Research Scholar and led several successful programs. He became a Fellow of the American Society of Mechanical Engineers in 2014. He is passionate about mentoring and team building with the goal of providing the Army the best possible technology to dominate today’s complex Multi-Domain Environment (MDE).

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Rahul Gupta

AI Research Scientist
US Army Laboratory

Dr. Rahul Gupta has been working at the Army Research Lab for more than a decade. In his current position he is conducting research and development using Deep Learning Artificial Neural Network and Convolutional Neural Network. He joined ARL as a Distinguished Research Scholar and led several successful programs. He became a Fellow of the American Society of Mechanical Engineers in 2014. He is passionate about mentoring and team building with the goal of providing the Army the best possible technology to dominate today’s complex Multi-Domain Environment (MDE).

Author:

Tom Sheffler

Solution Architect, Next Generation Sequencing
Former Roche

Tom earned his PhD from Carnegie Mellon in Computer Engineering with a focus on parallel computing architectures and prrogramming models.  His interest in high-performance computing took him to NASA Ames, and then to Rambus where he worked on accelerated memory interfaces for providing high bandwidth.  Following that, he co-founded the cloud video analytics company, Sensr.net, that applied scalable cloud computing to analyzing large streams of video data.  He later joined Roche to work on next-generation sequencing and scalable genomics analysis platforms.  Throughout his career, Tom has focused on the application of high performance computer systems to real world problems.

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Tom Sheffler

Solution Architect, Next Generation Sequencing
Former Roche

Tom earned his PhD from Carnegie Mellon in Computer Engineering with a focus on parallel computing architectures and prrogramming models.  His interest in high-performance computing took him to NASA Ames, and then to Rambus where he worked on accelerated memory interfaces for providing high bandwidth.  Following that, he co-founded the cloud video analytics company, Sensr.net, that applied scalable cloud computing to analyzing large streams of video data.  He later joined Roche to work on next-generation sequencing and scalable genomics analysis platforms.  Throughout his career, Tom has focused on the application of high performance computer systems to real world problems.

Hyperscaler
Emerging Memory Innovations
Cost/Power
AI/ML Compute
Moderator

Author:

Shyam Iyer

Distinguished Engineer & Member Of SNIA Technical Council
Dell
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Shyam Iyer

Distinguished Engineer & Member Of SNIA Technical Council
Dell
Speakers

Author:

David Kanter

Founder & Executive Director
MLCommons

David co-founded and is the Head of MLPerf for MLCommons, the world leader in building benchmarks for AI. MLCommons is an open engineering consortium with a mission to make AI better for everyone through benchmarks and data. The foundation for MLCommons began with the MLPerf benchmarks in 2018, which rapidly scaled as a set of industry metrics to measure machine learning performance and promote transparency of machine learning techniques. In collaboration with its 125+ members, global technology providers, academics, and researchers, MLCommons is focused on collaborative engineering work that builds tools for the entire AI industry through benchmarks and metrics, public datasets, and measurements for AI Safety. Our software projects are generally available under the Apache 2.0 license and our datasets generally use CC-BY 4.0.

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David Kanter

Founder & Executive Director
MLCommons

David co-founded and is the Head of MLPerf for MLCommons, the world leader in building benchmarks for AI. MLCommons is an open engineering consortium with a mission to make AI better for everyone through benchmarks and data. The foundation for MLCommons began with the MLPerf benchmarks in 2018, which rapidly scaled as a set of industry metrics to measure machine learning performance and promote transparency of machine learning techniques. In collaboration with its 125+ members, global technology providers, academics, and researchers, MLCommons is focused on collaborative engineering work that builds tools for the entire AI industry through benchmarks and metrics, public datasets, and measurements for AI Safety. Our software projects are generally available under the Apache 2.0 license and our datasets generally use CC-BY 4.0.

Author:

Dylan Patel

Chief Analyst
Semi Analysis
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Dylan Patel

Chief Analyst
Semi Analysis

Author:

Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

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Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

Author:

Helen Byrne

VP, Solution Architect
Graphcore

Helen leads the Solution Architects team at Graphcore, helping innovators build their AI solutions using Graphcore’s Intelligence Processing Units (IPUs). She has been at Graphcore for more than 5 years, previously leading AI Field Engineering and working in AI Research, working on problems in Distributed Machine Learning. Before landing in the technology industry, she worked in Investment Banking. Her background is in Mathematics and she has a MSc in Artificial Intelligence.

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Helen Byrne

VP, Solution Architect
Graphcore

Helen leads the Solution Architects team at Graphcore, helping innovators build their AI solutions using Graphcore’s Intelligence Processing Units (IPUs). She has been at Graphcore for more than 5 years, previously leading AI Field Engineering and working in AI Research, working on problems in Distributed Machine Learning. Before landing in the technology industry, she worked in Investment Banking. Her background is in Mathematics and she has a MSc in Artificial Intelligence.

Generative AI is reshaping compute and connectivity by pushing the limits of today's semiconductors. A new era of custom silicon designs has emerged, and is being embraced by all the major hyper-scalers. Chiplets in advanced 2.5D/3D packaging with high-speed interfaces such as HBM, UCIe, PCIe/CXL, and Ethernet have become key to address the critical challenges of memory bottlenecks for AI workloads. Learn how Alphawave Semi’s custom silicon and chiplet platforms are paving the way for unprecedented levels of performance, power efficiency, and scalability in AI-driven applications.

Author:

Mohit Gupta

SVP and GM, Custom Silicon and IP
Alphawave Semi

Mohit Gupta joined Alphawave Semi in September 2022 as part of the OpenFive acquisition from SiFive. He currently serves as Senior Vice President and General Manager for IP and Custom Silicon Business unit. Mohit brings in more than 2 decades of experience in semiconductor IP and SoC domains leading worldwide engineering, application engineering, products, and field teams. Prior to Alphawave Semi, he led the IP and Custom SoC business units at SiFive and Rambus.

Mohit holds a Bachelor of Engineering in Electronics and Communications from Thapar University and Master of Science in Microelectronics from BITS, Pilani. He also holds an executive MBA in International Business from Indian Institute of Management, Calcutta.

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Mohit Gupta

SVP and GM, Custom Silicon and IP
Alphawave Semi

Mohit Gupta joined Alphawave Semi in September 2022 as part of the OpenFive acquisition from SiFive. He currently serves as Senior Vice President and General Manager for IP and Custom Silicon Business unit. Mohit brings in more than 2 decades of experience in semiconductor IP and SoC domains leading worldwide engineering, application engineering, products, and field teams. Prior to Alphawave Semi, he led the IP and Custom SoC business units at SiFive and Rambus.

Mohit holds a Bachelor of Engineering in Electronics and Communications from Thapar University and Master of Science in Microelectronics from BITS, Pilani. He also holds an executive MBA in International Business from Indian Institute of Management, Calcutta.

Disaggregated memory is a promising approach that addresses the limitations of traditional memory architectures by enabling memory to be decoupled from compute nodes and shared across a data center. Cloud platforms have deployed such systems to improve overall system memory utilization, but performance can vary across workloads. High-performance computing (HPC) is crucial in scientific and engineering applications, where HPC machines also face the issue of underutilized memory. As a result, improving system memory utilization while understanding workload performance is essential for HPC operators. Therefore, learning the potential of a disaggregated memory system before deployment is a critical step. This paper proposes a methodology for exploring the design space of a disaggregated memory system. It incorporates key metrics that affect performance on disaggregated memory systems: memory capacity, local and remote memory access ratio, injection bandwidth, and bisection bandwidth, providing an intuitive approach to guide machine configurations based on technology trends and workload characteristics. We apply our methodology to analyze thirteen diverse workloads, including AI training, data analysis, genomics, protein, fusion, atomic nuclei, and traditional HPC bookends. Our methodology demonstrates the ability to comprehend the potential and pitfalls of a disaggregated memory system and provides motivation for machine configurations. Our results show that eleven of our thirteen applications can leverage injection bandwidth disaggregated memory without affecting performance, while one pays a rack bisection bandwidth penalty and two pay the system-wide bisection bandwidth penalty. In addition, we also show that intra-rack memory disaggregation would meet the application's memory requirement and provide enough remote memory bandwidth.

Systems Infrastructure/Architecture
HPC
Emerging Memory Innovations

Author:

Nan Ding

Research Scientist
Berkeley Research Lab

Nan Ding is a Research Scientist in the Performance and Algorithms group of the Computer Science Department at Lawrence Berkeley National Laboratory. Her research interests include high-performance computing, performance modeling and performance optimization. Nan received her Ph.D. in computer science from Tsinghua University, Beijing, China in 2018.

... read more

Nan Ding

Research Scientist
Berkeley Research Lab

Nan Ding is a Research Scientist in the Performance and Algorithms group of the Computer Science Department at Lawrence Berkeley National Laboratory. Her research interests include high-performance computing, performance modeling and performance optimization. Nan received her Ph.D. in computer science from Tsinghua University, Beijing, China in 2018.