Memory Systems Eng. | Kisaco Research

Memory Systems Eng.

Memory Systems Eng.

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Standard computer architectures suffer from von Neumann bottlenecks for all processing is done exclusively on the processor.
The computer's memory is not involved in processing, as it is only used to store programs and data. When a computing system or application has large amounts of data, moving data between memory and the processor can slow down processing.
Adding processing directly into memory can help alleviate this problem. Processing In Memory (PIM) or Processing Near Memory (PNM) is capable of manipulating data in computer memory.
By moving part of the computation to a memory device, PIM/PNM solves a fundamental problem in modern computing system design: the mismatch between von Neumann architectures and the huge memory bandwidth demanding of applications.
Many industrial prototypes and products are under development or are already available on the market, and these devices show promise for cost-effective and energy-efficient acceleration of HPC, AI, and Big-Data analytics workloads.
This panel will discuss the reasons for the renewed interest in PIM/PNM and its technological readiness and challenges in terms of Applications, System and SW.

Embedded Memory
Emerging Memories
Hardware Eng.
Memory Systems Eng.
Moderator

Author:

Seungwon Lee

VP of Technology (Master), Samsung Advanced Institute of Technology
Samsung Electronics

Seungwon Lee is a Master (VP of Technology) at Samsung, where he leads Computing SW Team at SAIT(Samsung Advanced Institute of Technology) of Samsung Electronics.

His research interests include large scale deep learning computing SW and In/Near memory computing SW.

Lee received a Ph.D degree in computer science and engineering from Seoul National University.

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Seungwon Lee

VP of Technology (Master), Samsung Advanced Institute of Technology
Samsung Electronics

Seungwon Lee is a Master (VP of Technology) at Samsung, where he leads Computing SW Team at SAIT(Samsung Advanced Institute of Technology) of Samsung Electronics.

His research interests include large scale deep learning computing SW and In/Near memory computing SW.

Lee received a Ph.D degree in computer science and engineering from Seoul National University.

Panellists

Author:

George Apostol

Founder & CEO
Elastics.cloud

George has over 35 years of experience designing system-on-chip (SoC), hardware, software, and systems. He holds several patents for interconnect and interface design and has led technology organizations developing products for several markets. He has held leadership and executive roles at Xerox/PARC, Sun, SGI, LSI Logic, Exar, and Samsung as well as start-ups including TiVo, BRECIS, Audience and BAYIS. As VP of Engineering and CTO at PLX Technology, George drove the development of  PCI Express switches, which are broadly used in the market today. He received his bachelor’s degree in Electrical Engineering from the Massachusetts Institute of Technology.

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George Apostol

Founder & CEO
Elastics.cloud

George has over 35 years of experience designing system-on-chip (SoC), hardware, software, and systems. He holds several patents for interconnect and interface design and has led technology organizations developing products for several markets. He has held leadership and executive roles at Xerox/PARC, Sun, SGI, LSI Logic, Exar, and Samsung as well as start-ups including TiVo, BRECIS, Audience and BAYIS. As VP of Engineering and CTO at PLX Technology, George drove the development of  PCI Express switches, which are broadly used in the market today. He received his bachelor’s degree in Electrical Engineering from the Massachusetts Institute of Technology.

Author:

Andy Mills

Senior Director, Advanced Product Development
SMART Modular Technologies

Andy Mills is the Snr Director of Advanced Product Development at SMART Modular Technologies, where he leads the development of next generation CXL memory and data center storage solutions.

 

Prior to joining SMART, Andy was CEO/co-founder of Enmotus, Inc where he co-developed and led the development of intelligent storage and memory tiering solutions for data center and high end PCs utilizing advanced learning algorithms driven by real time intelligent workload analysis. He has more than 30 years industry experience in software development, systems architecture, networking, storage and semiconductor development, plus held various management and technical lead positions at DotHill Systems, NetCell Corporation, TDK Semi, AMD.

 

Andy graduated with an MEng and BEng with Honors from Bangor University in the UK.

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Andy Mills

Senior Director, Advanced Product Development
SMART Modular Technologies

Andy Mills is the Snr Director of Advanced Product Development at SMART Modular Technologies, where he leads the development of next generation CXL memory and data center storage solutions.

 

Prior to joining SMART, Andy was CEO/co-founder of Enmotus, Inc where he co-developed and led the development of intelligent storage and memory tiering solutions for data center and high end PCs utilizing advanced learning algorithms driven by real time intelligent workload analysis. He has more than 30 years industry experience in software development, systems architecture, networking, storage and semiconductor development, plus held various management and technical lead positions at DotHill Systems, NetCell Corporation, TDK Semi, AMD.

 

Andy graduated with an MEng and BEng with Honors from Bangor University in the UK.

Author:

Seyong Lee

Senior R&D Staff
Oak Ridge National Laboratory

Seyong Lee is a Senior R&D Staff in the Computer Science and Mathematics Division at Oak Ridge National Laboratory (ORNL). His research interests include parallel programming and performance optimization in heterogeneous computing environments, program analysis, and optimizing compilers. He received his PhD in Electrical and Computer Engineering from Purdue University, USA.

He is a member of the OpenACC Technical Committee and a former member of the Seed Review Committee of the ORNL Seed Program and the NVIDIA PathForward Working Group of the Exascale Computing Project PathForward Program.

He served as a program committee/guest editor/external reviewer for various conferences, journals, and research proposals.

His paper on SC10 won the best student paper award, and his paper on PPoPP09 was selected as the most cited paper among all papers published in PPoPP between 2009 and 2014.

He received the IEEE Computer Society TCHPC Award for Excellence for Early Career Researchers in High Performance Computing at SC16 and served as an award committee member for 2017 IEEE CS TCHPC Award. 

See his website for more information: https://seyonglee.github.io.

... read more

Seyong Lee

Senior R&D Staff
Oak Ridge National Laboratory

Seyong Lee is a Senior R&D Staff in the Computer Science and Mathematics Division at Oak Ridge National Laboratory (ORNL). His research interests include parallel programming and performance optimization in heterogeneous computing environments, program analysis, and optimizing compilers. He received his PhD in Electrical and Computer Engineering from Purdue University, USA.

He is a member of the OpenACC Technical Committee and a former member of the Seed Review Committee of the ORNL Seed Program and the NVIDIA PathForward Working Group of the Exascale Computing Project PathForward Program.

He served as a program committee/guest editor/external reviewer for various conferences, journals, and research proposals.

His paper on SC10 won the best student paper award, and his paper on PPoPP09 was selected as the most cited paper among all papers published in PPoPP between 2009 and 2014.

He received the IEEE Computer Society TCHPC Award for Excellence for Early Career Researchers in High Performance Computing at SC16 and served as an award committee member for 2017 IEEE CS TCHPC Award. 

See his website for more information: https://seyonglee.github.io.

Author:

Nuwan Jayasena

Fellow
AMD

Nuwan Jayasena is a Fellow at AMD Research, and leads a team exploring hardware support, software enablement, and application adaptation for processing in memory. His broader interests include memory system architecture, accelerator-based computing, and machine learning. Nuwan holds an M.S. and a Ph.D. in Electrical Engineering from Stanford University and a B.S. from the University of Southern California. He is an inventor of over 70 US patents, an author of over 30 peer-reviewed publications, and a Senior Member of the IEEE. Prior to AMD, Nuwan was a processor architect at Nvidia Corp. and at Stream Processors, Inc.

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Nuwan Jayasena

Fellow
AMD

Nuwan Jayasena is a Fellow at AMD Research, and leads a team exploring hardware support, software enablement, and application adaptation for processing in memory. His broader interests include memory system architecture, accelerator-based computing, and machine learning. Nuwan holds an M.S. and a Ph.D. in Electrical Engineering from Stanford University and a B.S. from the University of Southern California. He is an inventor of over 70 US patents, an author of over 30 peer-reviewed publications, and a Senior Member of the IEEE. Prior to AMD, Nuwan was a processor architect at Nvidia Corp. and at Stream Processors, Inc.

Author:

Paul Crumley

Senior Technical Staff Member
IBM Research

Paul G Crumley, a Senior Technical Staff Member at IBM Research, enjoys creating systems to solve problems beyond the reach of current technology.

 

Paul’s current project integrates secure, compliant AI capabilities with enterprise Hybrid Cloud allowing clients to extract new business value from their data.

 

Paul’s previous work includes the design and construction of distributed, and high-performance computing systems at CMU, Transarc, and IBM Research. Projects include The Andrew Project at CMU, ASCI White, IBM Global Storage Architecture, Blue Gene Supercomputers, IBM Cloud, and IBM Cognitive Systems. Paul has managed data centers, and brings his first-hand knowledge of these environments, combined with experience of automation and robustness, to the design of AI for Hybrid Cloud infrastructure.

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Paul Crumley

Senior Technical Staff Member
IBM Research

Paul G Crumley, a Senior Technical Staff Member at IBM Research, enjoys creating systems to solve problems beyond the reach of current technology.

 

Paul’s current project integrates secure, compliant AI capabilities with enterprise Hybrid Cloud allowing clients to extract new business value from their data.

 

Paul’s previous work includes the design and construction of distributed, and high-performance computing systems at CMU, Transarc, and IBM Research. Projects include The Andrew Project at CMU, ASCI White, IBM Global Storage Architecture, Blue Gene Supercomputers, IBM Cloud, and IBM Cognitive Systems. Paul has managed data centers, and brings his first-hand knowledge of these environments, combined with experience of automation and robustness, to the design of AI for Hybrid Cloud infrastructure.

•        Computational Storage and Memory

•        CXL and UCIe 

•        Emerging Persistent Memory Types 

•        Bridging to the Application Layer 

Use Case
Embedded Memory
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Tom Coughlin

President
Coughlin Associates

Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant.  He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.

Dr. Coughlin has many publications and six patents to his credit.  Tom is also the author of Digital Storage in Consumer Electronics:  The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services.  Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports.  Tom is also a regular contributor on digital storage for Forbes.com and other blogs.

Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations.  Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years.  He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV).  For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.

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Tom Coughlin

President
Coughlin Associates

Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant.  He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.

Dr. Coughlin has many publications and six patents to his credit.  Tom is also the author of Digital Storage in Consumer Electronics:  The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services.  Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports.  Tom is also a regular contributor on digital storage for Forbes.com and other blogs.

Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations.  Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years.  He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV).  For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.

Author:

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA
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David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

Author:

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

... read more

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Author:

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

... read more

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Author:

Arthur Sainio

Director, Product Marketing
Smart Modular Technologies

Arthur Sainio is Co-Chair of the SNIA Persistent Memory and NVDIMM Special Interest Group, which accelerates the awareness and adoption of Persistent Memories and NVDIMMs for computing architectures.

As a Director of Product Marketing at SMART Modular Technologies. Arthur has been driving new product launch and business development activities at SMART since 1998.

Prior to Smart, Arthur worked as a product manager at Hitachi Semiconductor America. While there, his focus was on DRAM, SRAM, and Flash technologies.

Arthur holds a MBA from San Francisco State University and a MS from Arizona State
University.

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Arthur Sainio

Director, Product Marketing
Smart Modular Technologies

Arthur Sainio is Co-Chair of the SNIA Persistent Memory and NVDIMM Special Interest Group, which accelerates the awareness and adoption of Persistent Memories and NVDIMMs for computing architectures.

As a Director of Product Marketing at SMART Modular Technologies. Arthur has been driving new product launch and business development activities at SMART since 1998.

Prior to Smart, Arthur worked as a product manager at Hitachi Semiconductor America. While there, his focus was on DRAM, SRAM, and Flash technologies.

Arthur holds a MBA from San Francisco State University and a MS from Arizona State
University.

CPU performance improvement based on Dennard scaling and Moore's Law has already reached its limit, and domain-specific computing was considered as an alternative to overcome the limitations of the existing CPU-centric computing model. Domain-specific computing, seen in early graphics and network cards, has expanded into accelerators such as GPGPUS, TPUs, FPGAS, and IDPs. Meanwhile, hyperscalers, where power efficiency is particularly important, use ASICs or FPGAs to offload and accelerate OS, security, and data processing tasks. Handling large amounts of data in a power-efficient manner requires reexamining the model for moving data from traditional storage to the CPU. This model consumes a lot of power and limits performance due to bandwidth limitations. Computer Storage (CS) or In-Storage Computing (ISC), first explored in the 1990s, is another important piece of the puzzle. As data is explosively generated in the cloud, machine learning, big data, and edge, the industry is actively reviewing the application of CS in various fields. This panel discusses the current state of CS, its potentials and challenges in various applications.

Emerging Memories
Embedded Memory
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Yang Seok Ki

CXL Board of Director, VP and CTO of Memory Solutions Lab
Samsung Electronics

Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a CXL board of director and a technical chair of Data Centric Computing workstream of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.

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Yang Seok Ki

CXL Board of Director, VP and CTO of Memory Solutions Lab
Samsung Electronics

Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a CXL board of director and a technical chair of Data Centric Computing workstream of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.

Panellists

Author:

Stephen Bates

VP & Chief Architect, Emerging Storage Systems
Huawei

Stephen is the VP and  Chief Architect of Emerging Storage Systems at Huawei's Toronto Emerging Storage Lab. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.

Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. He is also very active in both the SNIA and NVM Express standard bodies.

Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. He was also formerly in the CTO office at PMC-Sierra, an Assistant Professor at The Univeristy of Alberta and a Principal Engineer at Massana Inc. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

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Stephen Bates

VP & Chief Architect, Emerging Storage Systems
Huawei

Stephen is the VP and  Chief Architect of Emerging Storage Systems at Huawei's Toronto Emerging Storage Lab. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.

Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. He is also very active in both the SNIA and NVM Express standard bodies.

Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. He was also formerly in the CTO office at PMC-Sierra, an Assistant Professor at The Univeristy of Alberta and a Principal Engineer at Massana Inc. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Author:

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

... read more

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Author:

Seong Kim

Senior Director, Datacenter Solutions Architect
AMD

As the leader of the global data center solutions architect group at AMD, Seong is focused on driving the development of data center application acceleration and offload for compute, network, and storage solutions. Seong’s recent focuses are on smart video analytics, machine learning, database acceleration, smart NIC, smart SSD and computational storage accelerations.

 

Seong holds a Ph.D. in Electrical and Computer Engineering and an MBA in Marketing. He has authored numerous technical papers, white papers, and patents, and has presented industry seminars. Throughout his career, Seong has developed proof-of-concept solutions for data center, wireless, and wireline applications using network processors, FPGA, x86 & ARM, and networking peripherals. He is proactively recommending courses of action to bring competitiveness to the solutions and defining the roadmap and next-generation platforms.

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Seong Kim

Senior Director, Datacenter Solutions Architect
AMD

As the leader of the global data center solutions architect group at AMD, Seong is focused on driving the development of data center application acceleration and offload for compute, network, and storage solutions. Seong’s recent focuses are on smart video analytics, machine learning, database acceleration, smart NIC, smart SSD and computational storage accelerations.

 

Seong holds a Ph.D. in Electrical and Computer Engineering and an MBA in Marketing. He has authored numerous technical papers, white papers, and patents, and has presented industry seminars. Throughout his career, Seong has developed proof-of-concept solutions for data center, wireless, and wireline applications using network processors, FPGA, x86 & ARM, and networking peripherals. He is proactively recommending courses of action to bring competitiveness to the solutions and defining the roadmap and next-generation platforms.

Author:

Keith McKay

Senior Director
ScaleFlux
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Keith McKay

Senior Director
ScaleFlux

Author:

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA
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David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

Author:

Jongryool Kim

Research Director
SK Hynix

Jongryool Kim is currently a research director overseeing next generation architecture enablement at SK hynix where his team’s main responsibilities are to research and to fast-prototype new data storage technologies such as computational memory and storage solutions. Prior to this role, he worked with various R&D teams at Samsung’s SW R&D Center.

In addition, he had served as the key engineer and development manager on the data analytics system of Samsung Cloud at Samsung Mobile division. He earned his Ph.D degree in Computer Engineering form GIST, South Korea.

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Jongryool Kim

Research Director
SK Hynix

Jongryool Kim is currently a research director overseeing next generation architecture enablement at SK hynix where his team’s main responsibilities are to research and to fast-prototype new data storage technologies such as computational memory and storage solutions. Prior to this role, he worked with various R&D teams at Samsung’s SW R&D Center.

In addition, he had served as the key engineer and development manager on the data analytics system of Samsung Cloud at Samsung Mobile division. He earned his Ph.D degree in Computer Engineering form GIST, South Korea.

High-throughput, low latency data movement between compute resources (memory included) has become a bottleneck in modern distributed computing workloads such as AI/ML, HPC, and databases. The interconnect fabrics for the two main types of data movement in compute - load store memory access and byte moving I/O - have historically been built and treated disparately. While this made sense when CPU I/O and network interfaces were far lower bandwidth than memory interfaces, their interconnect is now at an architectural merge point. In this keynote, Enfabrica will reveal its blueprint for any-scale, high-bandwidth, latency-tiered memory movement in the data center based on fabrics that blend load store and local DMA primitives (over CXL, PCIe, and similar) with RDMA over network technologies running at 800 Gbps and beyond. We will highlight the efficiencies of such a unified fabric architecture, its ability to render high-throughput memory movement as scalable and hierarchical from chipset to cluster, and its utility as an infrastructure building block that fits seamlessly within existing, robust system software frameworks.

Embedded Memory
Emerging Memories
External Memory
Use Case
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Shrijeet Mukherjee

Co-Founder & Chief Development Officer
Enfabrica

Shrijeet is a Co-Founder and the Chief Development Officer of Enfabrica. Prior to founding Enfabrica, he was an architect in Google’s infrastructure group. Previously, he was VP Engineering at Cumulus Networks where he built the industry’s first disaggregated Linux-native network operating system. He was the software engineering leader and architect of the industry’s first virtualization/storage offload “smart-NICs” for Cisco UCS. At SGI he was part of the Advanced Graphics team that pioneered floating point framebuffers and programmable shaders. Shrijeet is on the Linux NetDev Society Board of Directors and has over 20 patents. He holds an MS in Computer Science from the University of Oregon.

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Shrijeet Mukherjee

Co-Founder & Chief Development Officer
Enfabrica

Shrijeet is a Co-Founder and the Chief Development Officer of Enfabrica. Prior to founding Enfabrica, he was an architect in Google’s infrastructure group. Previously, he was VP Engineering at Cumulus Networks where he built the industry’s first disaggregated Linux-native network operating system. He was the software engineering leader and architect of the industry’s first virtualization/storage offload “smart-NICs” for Cisco UCS. At SGI he was part of the Advanced Graphics team that pioneered floating point framebuffers and programmable shaders. Shrijeet is on the Linux NetDev Society Board of Directors and has over 20 patents. He holds an MS in Computer Science from the University of Oregon.

CXL
Embedded Memory
Emerging Memories
External Memory
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

... read more

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Embedded Memory
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Jin-Hyeok Choi

EVP, Memory Solution & Product Development
Samsung Electronics

Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.

Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.

Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.

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Jin-Hyeok Choi

EVP, Memory Solution & Product Development
Samsung Electronics

Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.

Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.

Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.

Over the last two decades, large HPC machine efforts have become a procurement exercise.  A large set of applications have been unable to leverage the additional computational power of newly-procured machines without significant additional software development.  The machine architectures need to evolve:  new systems architectures and innovations require a deep understanding of application uses cases and their needs.   Memory and storage, as foundational elements, will be at the center of future innovative systems, driving both greater performance and increased energy efficiency.

CXL
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Steve Pawlowski

CVP, Advanced Memory Systems
Micron

Steve Pawlowski is corporate vice president of advanced computing solutions at Micron Technology. He is responsible for defining and developing innovative memory solutions for the enterprise and high performance computing markets.

Prior to joining Micron in July 2014, Steve was a senior fellow and the chief technology officer for Intel’s Data Center and Connected Systems Group. His extensive industry experience includes 31 years at Intel, where he held several high-level positions and led teams in the design and development of next-generation system architectures and computing platforms.

Steve earned bachelor’s degrees in electrical engineering and computer systems engineering technology from the Oregon Institute of Technology and a master’s degree in computer science and engineering from the Oregon Graduate Institute. He also holds 58 patents.

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Steve Pawlowski

CVP, Advanced Memory Systems
Micron

Steve Pawlowski is corporate vice president of advanced computing solutions at Micron Technology. He is responsible for defining and developing innovative memory solutions for the enterprise and high performance computing markets.

Prior to joining Micron in July 2014, Steve was a senior fellow and the chief technology officer for Intel’s Data Center and Connected Systems Group. His extensive industry experience includes 31 years at Intel, where he held several high-level positions and led teams in the design and development of next-generation system architectures and computing platforms.

Steve earned bachelor’s degrees in electrical engineering and computer systems engineering technology from the Oregon Institute of Technology and a master’s degree in computer science and engineering from the Oregon Graduate Institute. He also holds 58 patents.

CXL as memory expansion is changing how data centers think about main memory.  Direct attached memory on DIMMs has flattened out, with DDR5 barely extending the footprint of older DDR4 systems at the same time that artificial intelligence and similar applications are demanding massive increases in total memory capacity.  CXL memory modules can dramatically grow the memory footprint, however CXL introduces new challenges that have users concerned.  Increased power requirements, longer access latency, limited per-module capacity, and increased danger of data loss on power failure have end users wondering… is it really worth it?  Non-volatile main memory can address these limitations of CXL memory expansion, encouraging data centers to lay the foundation for a future with whole new ways to think about memory pooling.

CXL
Embedded Memory
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

... read more

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

CXL
Emerging Memories
External Memory
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

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Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

Panellists

Author:

Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

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Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

Author:

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

... read more

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

Author:

Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

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Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

Author:

Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

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Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Author:

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

... read more

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

CXL
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

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Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.